The present invention relates to semiconductor design technology, particularly, to an internal voltage generator of a semiconductor device, and more particularly, to a circuit capable of generating an internal voltage with stable voltage level variation.
Most semiconductor devices including DRAMs employ an internal voltage generator in a chip so as to generate internal voltages with various levels using a power supply voltage (VDD) and a ground voltage (VSS) applied from outside the device, thereby supplying a voltage required for operating internal circuits in the chip itself. A main issue in designing such an internal voltage generator is to stably supply an internal voltage with a desired level.
Recently, studies are being conducted on semiconductor devices with low power consumption as well as high-speed performance. Accordingly, a new design technology is required to meet the performance required under a low voltage condition. Under such a low voltage condition, most semiconductor devices need a boosted voltage (VPP) having a higher voltage level than a power supply voltage (VDD) so as to compensate for a voltage loss occurring when it operates using the power supply voltage (VDD), and to retain data normally.
In particular, DRAMs widely use the boosted voltage (VPP) for compensating loss caused by a threshold voltage of an MOS transistor in a word line driving circuit, a signal line separating circuit, a data output buffer circuit, and so forth.
In DRAMs, a back bias voltage (VBB) having a lower voltage than a ground voltage (VSS) is applied to a bulk of an NMOS transistor used as a cell transistor.
Since the boosted voltage (VPP) and the back bias voltage (VBB) are generated in a charge-pumping manner and they are thus generated through the same generation mechanism, circuits for generating them can be similarly configured.
FIG. 1 is a block diagram illustrating a conventional internal voltage generator of a semiconductor device.
Referring to FIG. 1, the conventional internal voltage generator of the semiconductor device includes a voltage level detector 100, an oscillator 120 and a pump 160. The voltage level detector 100 detects a voltage level of an internal voltage (VPP) terminal to output a detection signal PPE. The oscillator 120 generates an oscillation signal OSC of a predetermined frequency in response to the detection signal PPE. The pump 160 performs a charge pumping operation to output an internal voltage VPP to the internal voltage (VPP) terminal in response to the oscillation signal OSC.
FIG. 2A is a circuit diagram illustrating the voltage level detector 100 of FIG. 1.
Referring to FIG. 2A, the voltage level detector 100 of the conventional internal voltage generator includes a voltage divider 102 for dividing the internal voltage VPP by a predetermined ratio to thereby generate a division voltage DIV_VPP, and a voltage comparator 104 for comparing the division voltage DIV_VPP with a reference voltage VREF and outputting the detection signal PPE of which a logic level is determined according to the comparison result.
The voltage divider 102 includes a first fixed resistor R1 and a second fixed resistor R2 which have predetermined resistances and are connected in series between the internal voltage (VPP) terminal and a ground voltage (VSS) terminal. The voltage divider 102 generates the division voltage DIV_VPP through a connection node between the first and second fixed resistors R1 and R2.
The voltage comparator 104 includes a unit amplifier 1042 for changing a level of a voltage applied to an output terminal OUTN corresponding to a level difference between the division voltage DIV_VPP and the reference voltage VREF, and a driver 1044 for outputting the detection signal PPE corresponding to a level of a voltage applied to the output terminal OUTN.
The unit amplifier 1042 of the voltage comparator 104 includes first and second PMOS transistors P1 and P2 connected to each other in a current mirror form, a first NMOS transistor N1 for receiving the division voltage DIV_VPP through a gate thereof, a second NMOS transistor N2 for receiving the reference voltage VREF through a gate thereof, and a third NMOS transistor N3 used as a current source of the unit amplifier 1042 in response to a bias voltage.
The driver 1044 of the voltage comparator 104 includes at least one inverter INV for determining a logic level of the detection signal PPE outputted on the basis of a predetermined logic threshold voltage level corresponding to the level of the voltage applied to the output terminal OUTN of the unit amplifier 1042.
Herein, a detectable level of a logic level variation is defined as the logic threshold voltage level. That is, the logic level of the detection signal PPE is determined by comparing a level of the voltage applied to the output terminal OUTN of the unit amplifier 1042 with the logic threshold voltage level.
FIG. 2B is a circuit diagram illustrating the oscillator 120 of FIG. 1.
Referring to FIG. 2B, the oscillator 120 of the conventional internal voltage generator includes a NAND gate NAND, a first inverter chain 122 and a second inverter chain 124. The NAND gate NAND performs a NAND operation on the detection signal PPE and a feedback signal FBS. The first inverter chain 122 inverts an output signal of the NAND gate NAND to output the oscillation signal OSC. The second inverter chain 124 inverts the oscillation signal OSC to output the feedback signal FBS.
Herein, the first inverter chain 122 includes odd number of inverters, for example, three inverters INT1, INT2 and INT3. Herein, the number of the inverters provided in the first inverter chain 122 is at least one or more.
Likewise, the second inverter chain 124 includes odd number of inverters, for example, three inverters INT4, INT5 and INT6. Herein, the number of the inverters provided in the second inverter chain 124 is at least one or more.
An operation of the conventional internal voltage generator having the above construction will be described below.
The voltage level detector 100 compares a voltage level of the internal voltage VPP feedback from the internal voltage (VPP) terminal of the pump 160 with a voltage level of the reference voltage VREF, thereby outputting the detection signal PPE.
For example, when the internal voltage VPP has a lower voltage level than the reference voltage VREF, the magnitude of current flowing through a drain-source path of the first NMOS transistor N1 is smaller than the magnitude of current flowing through a drain-source path of the second NMOS transistor N2. Here, a resistance of the first NMOS transistor N1 changes in response to the division voltage DIV_VPP obtained by dividing the internal voltage VPP by the predetermined ratio, and a resistance of the second NMOS transistor N2 changes in response to the reference voltage VREF.
Therefore, a level of a voltage applied to an input node ZN is higher than a level of a voltage applied to an output node OUTN. When the level of the voltage applied to the output node OUTN becomes lower than the logic threshold voltage level of the driver 1044, the activated detection signal PPE of logic high level is generated.
When the internal voltage has a higher voltage level than the reference voltage VREF, the magnitude of current flowing through the drain-source path of the first NMOS transistor N1 is greater than the magnitude of current flowing through the drain-source path of the second NMOS transistor N2. Likewise, the resistance of the first NMOS transistor N1 changes in response to the division voltage DIV_VPP obtained, and the resistance of the second NMOS transistor N2 changes in response to the reference voltage VREF.
Accordingly, the level of the voltage applied to the input node ZN is lower than the level of the voltage applied to the output node OUTN. That is, the level of the voltage applied to the output node OUTN increases to be higher than the logic threshold voltage level of the driver 1044, and thus the deactivated detection signal PPE of logic low level is generated.
An activation section of the detection signal PPE may differ corresponding to a level difference between the internal voltage VPP and the reference voltage VREF.
That is, when the level difference between the internal voltage VPP and the reference voltage VREF is relatively great, the detection signal PPE with a relatively long activation section is generated. On the contrary, when the level difference between the internal voltage VPP and the reference voltage VREF is relatively small, the detection signal PPE with a relatively short activation section is generated.
A method of comparing the division voltage DIV_VPP, which is obtained by diving the internal voltage VPP by a predetermined ratio, with the reference voltage VREF is employed herein, but this method is just one of several methods of comparing the internal voltage VPP with the reference voltage VREF.
The reference voltage VREF is generated by a bandgap circuit, and maintains a target level of the internal voltage VPP irrespective of variations of process, voltage and temperature (PVT).
The oscillator 120 generates the oscillation signal OSC oscillating at a predetermined frequency in response to a logic level of the detection signal PPE inputted from the voltage level detector 100.
For instance, when the activated detection signal PPE of logic high level is inputted, the oscillation signal OSC oscillates at the predetermined frequency. On the contrary, when the deactivated detection signal PPE of logic low level is inputted, the oscillation signal OSC does not oscillate but maintains the deactivation state of logic low level.
In other words, when the internal voltage VPP has a lower voltage level than the reference voltage VREF, the oscillation signal OSC oscillates at a predetermined frequency; and when the internal voltage VPP has a higher voltage level than the reference voltage VREF, the oscillation signal OSC does not oscillate but maintains the deactivation state of logic low level.
When the inputted oscillation signal OSC oscillates at the predetermined frequency, the pump 160 performs a charge pumping operation to generate the internal voltage VPP. When, however, the oscillation signal OSC does not oscillate but is under a deactivation state, the pump 160 does not perform a charge pumping operation thereby not to generate the internal voltage VPP.
That is, the pump 160 performs a charge pumping operation to generate the internal voltage VPP when the level of the internal voltage VPP is lower than that of the reference voltage VREF. Contrariwise, the pump 160 does not perform the charge pumping operation and does not generate the internal voltage VPP when the level of the internal voltage VPP is higher than that of the reference voltage VREF.
From the aforesaid operation of the conventional internal voltage generator of the semiconductor device, it can be appreciated that the charge pumping operation is performed to increase the level of the internal voltage VPP when the level of the internal voltage VPP is lower than the level of the reference voltage VREF; but the pump 160 does not work to wait for the level of the internal voltage VPP to be lower than the level of the reference voltage VREF. The level of the internal voltage VPP may become lower than the level of the reference voltage VREF if the internal voltage VPP is used for a predetermined operation of the semiconductor device or charges are naturally discharged.
In the conventional internal voltage generator, the method of detecting the voltage level of the internal voltage (VPP) terminal using the voltage level detector 100 was adopted for detecting the level of the internal voltage VPP.
However, in order that the voltage level detector 100 may detect the level of the internal voltage VPP to output the detection signal PPE, several operations should be performed, including: dividing the internal voltage VPP by the predetermined ratio to output the division voltage DIV_VPP; comparing the voltage level of the division voltage DIV_VPP with that of the reference voltage VREF; and determining a logic level of the detection signal PPE corresponding to the comparison result. Therefore, it takes a lot of time to perform the above-described processes.
Like this, if the time taken for the voltage level detector 100 to determine the logic level of the detection signal VPP corresponding to the variation of the voltage level of the internal voltage (VPP) terminal is elongated, it gives rise to problems as follows.
FIG. 3 is a timing diagram illustrating a voltage level variation of the internal voltage generated by the conventional internal voltage generator of FIG. 1.
From FIG. 3, it can be appreciated that a level variation of the internal voltage generated by the conventional internal voltage generator of FIG. 1 is relatively high.
Specifically, when the voltage level detector 100 detects, at an initial state, that the level of the internal voltage VPP is lower than a target level of the internal voltage VPP, the detection signal PPE is activated to logic high level to increase the level of the internal voltage VPP through the charge pumping operation of the pump 160 ({circle around (1)}).
When the level of the internal voltage VPP which is rising up is greater than the target level, the voltage level detector 100 detects it so that the charge pumping operation of the pump 160 must be stopped by deactivating the detection signal PPE to logic low level.
In the conventional internal voltage generator of the semiconductor device, however, the time taken for the voltage level detector 100 to determine the logic level of the detection signal VPP is relatively long, the voltage level detector 100 cannot promptly deactivate the detection signal PPE to logic low level at the instant that the level of the internal voltage VPP is greater than the target level of the internal voltage VPP. Resultingly, the charge pumping operation of the pump 160 is not promptly stopped so that the voltage level of the internal voltage VPP still increases to a relatively higher level than the target level ({circle around (2)}).
Therefore, the voltage level of the internal voltage VPP increases excessively, which affects an operating speed of a semiconductor device, leading to an unstable operation of the semiconductor device.
Moreover, there is a great likelihood that the semiconductor device using such an internal voltage VPP may operate unpredictably. That is, the semiconductor device cannot operate reliably.
In order to increase a processing speed of the voltage level detector 100 in the internal voltage generator of the semiconductor device, the amount of driving current for driving the voltage level detector 100 may be increased. This, however, causes the voltage level detector 100 to unnecessarily consume a lot of driving current even during a stand-by mode when the voltage level detector 100 does not operate, and thus it is not suitable for a state-of-the-art semiconductor device that has to use smaller and smaller amount of driving current.